The semiconductor industry is moving toward increasing device complexity, requiring shrinking geometric dimensions and higher component integration with greater dimensional densities in integrated circuit devices, e.g. memory and logic chips. This has led to an increase in the number of wiring levels and a reduction in the wiring pitch to increase the wiring density. Current leading-edge logic processors have 6-7 levels of high density interconnect, and interconnect line width is scheduled to decrease to 0.1 μm around the year 2005.
As device dimensions shrink to less than 0.25 μm, the propagation delay, crosstalk noise, and power dissipation due to resistance-capacitance (RC) coupling become significant. The smaller line dimension increases the resistivity of metal wires, and the narrow intermetal spacing increases the capacitance between the metal wires. Thus although the speed of the device will increase as the feature size decreases, the interconnect delay becomes the major fraction of the total delay and limits the overall chip performance. Accordingly, in order to prepare a chip having high speed, a conductor having a low resistance and a dielectric material having low dielectric constant should be used. In addition, the use of low dielectric material can remarkably decrease the power dissipation and crosstalk noise.
Recently, several semiconductor device manufacturers have put test products on the market that show improvement in their performance of 20% or more, using copper wiring with high electric conductivity instead of using the conventional aluminum wiring. Recently they shift to use of new materials that exhibit low dielectric constant performance, for use in interconnects. If the dielectric films between interconnect layers in integrated circuit can make use of these materials, the effect on operating speed will be the same as that which resulted with the switch from aluminum to copper technology. For instance, if the dielectric constant of the dielectric material is changed from 4.0 to about 2.5, IC operating speed will be improved by about 20%.
The interlayer dielectric material used in semiconductor integrated circuit devices is predominantly SiO2, which is generally formed using chemical vapor deposition (CVD) or plasma enhanced techniques and has the requisite mechanical and thermal properties to withstand various processing operations associated with semiconductor manufacturing. The relative dielectric constant of a SiO2 material varies with the conditions under which a dielectric is formed; that of silicon thermal oxidation films, which have the lowest dielectric constant, is on the order of 4.0. Attempts have been made to reduce the dielectric constant by introducing fluorine atoms into an inorganic film deposited by CVD. However, the introduction of fluorine atoms in large amounts decreases the chemical and thermal stability, so the dielectric constant achieved in actual practice is on the order of 3.5. Fluorinated oxides can provide an immediate near-term solution and a shift to new types of insulating materials with sub-3 dielectric constant may be required.
One class of candidates is organic polymers, some of which have a dielectric constant of less than 3.0. Incorporating fluorine into such organic polymer is known to further lower the dielectric constant. Most organic polymers do not, however, possess the physico-chemical properties required for on-chip semiconductor insulation, particularly thermal stability and mechanical properties (sufficient to withstand back end of the line fabrication temperatures within the range of 400˜450° C.). Few organic polymers are stable at temperatures greater than 450° C. They also have a low glass transition temperature and thus elasticity thereof remarkably decreases at high temperature, and they have a very high linear expansion coefficient. Since temperature rises to up to 450° C. during semiconductor IC integration and packaging processes, the resulting low thermal stability and elasticity and high linear expansion coefficient can deteriorate the reliability of the device.
Recently in order to solve thermal stability problems of organic polymers, the development of organic silicate polymers using a sol-gel process has emerged. In particular, organic SOG (Spin On Glass) has been proposed for use as interlayer dielectrics in which the side chain of an organic component (an alkyl group such as methyl) is bonded to the backbone chain of a siloxane bond. While having a lower dielectric constant, e.g., the range of about 2.7˜3.2, than conventional glasses, such materials typically have poor mechanical properties. For instance, methylsilsesquioxnane polymer experiences crack formation during processing unless the film is very thin (often <1 μm).
Miller et al. have reported a method of toughening the silsesquioxane material systems by incorporating a small amount of polymeric substituents such as a polyimide. A method of mixing an inorganic fine particulate powder is also known as another method for improving the mechanical properties of organosilicates. Although various systems have been proposed, there remains a need for a material having a suitable low dielectric constant and appropriate physico-chemical properties for use as an interlayer dielectric in the future generation of IC devices.